7.8 Transient Analysis with PSpice

← Back to Fundamentals of Electric Circuits Overview

7.8 Transient Analysis with PSpice

As we discussed in Section 7.5, the transient response is the temporary response of the circuit that soon disappears. PSpice can be used to obtain the transient response of a circuit with storage elements. Section D.4 in Appendix D provides a review of transient analysis using PSpice for Windows. It is recommended that you read Section D.4 before continuing with this section.

If necessary, dc PSpice analysis is first carried out to determine the initial conditions. Then the initial conditions are used in the transient PSpice analysis to obtain the transient responses. It is rec om mended but not necessary that during this dc analysis, all capac itors should be opencircuited while all inductors should be short-circuited.

Practice Problem 7.16

Figure 7.62 For Practice Prob. 7.16.

PSpice uses “transient” to mean “function of time.” Therefore, the transient response in PSpice may not actually die out as expected.

Use PSpice to find the response i(t) for t > 0 in the circuit of Fig. 7.63. Example 7.17

Solution:

Solving this problem by hand gives i(0) = 0, i(∞) = 2A, RTh = 6, τ = 3∕6 = 0.5 s, so that

$$i(t) = i(\infty) + [i(0) - i(\infty)]e^{-t/\tau} = 2(1 - e^{-2t}), \qquad t > 0$$

To use PSpice, we first draw the schematic as shown in Fig. 7.64. We recall from Appendix D that the part name for a closed switch is Sw_tclose. We do not need to specify the initial condition of the induc tor because PSpice will determine that from the circuit. By selecting Analysis/Setup/Transient, we set Print Step to 25 ms and Final Step to 5τ = 2.5 s. After saving the circuit, we simulate by selecting Analysis/ Simulate. In the PSpice A/D window, we select Trace/Add and display –I(L1) as the current through the inductor. Figure 7.65 shows the plot of i(t), which agrees with that obtained by hand calculation.

Figure 7.64 The schematic of the circuit in Fig. 7.63.

Figure 7.63 For Example 7.17.

Figure 7.65 For Example 7.17; the response of the circuit in Fig. 7.63.

Answer: v(t) = 8(1 − e^−t

that in Fig. 7.65.

Note that the negative sign on I(L1) is needed because the current enters through the upper terminal of the inductor, which happens to be the negative terminal after one counterclock wise rotation. A way to avoid the negative sign is to ensure that current enters pin 1 of the inductor. To obtain this desired direction of positive current flow, the initially horizontal inductor symbol should be rotated counterclockwise 270° and placed in the desired location.

) V, t > 0. The response is similar in shape to

For the circuit in Fig. 7.66, use Pspice to find v(t) for t > 0.

Practice Problem 7.17

Figure 7.66 For Practice Prob. 7.17.

12 Ω 30 V 6 Ω 6 Ω 3 Ω 0.1 F 4 A ⁺ ‒ ^t=^{0 t}=⁰ (a) ^v(t) + ‒ 6 Ω 6 Ω 12 Ω 0.1 F + v(t) ‒ 30 V (b) 10 Ω 0.1 F + v(t) ‒ 10 V (c) + ‒ + ‒ Example 7.18 In the circuit of Fig. 7.67(a), determine the response v(t).

Figure 7.67 For Example 7.18. Original circuit (a), circuit for t > 0 (b), and reduced circuit for t > 0 (c).

Solution:

• 1. Define. The problem is clearly stated and the circuit is clearly labeled.
• 2. Present. Given the circuit shown in Fig. 7.67(a), determine the response v ( t).
• 3. Alternative. We can solve this circuit using circuit analysis techniques, nodal analysis, mesh analysis, or PSpice. Let us solve the problem using circuit analysis techniques (this time Thevenin equivalent circuits) and then check the answer using two methods of PSpice .
• 4. Attempt. For time < 0, the switch on the left is open and the switch on the right is closed. Assume that the switch on the right has been closed long enough for the circuit to reach steady state; then the capacitor acts like an open circuit and the current from the 4-A source flows through the parallel combination of the 6- Ω and 3-Ω resistors (6 ∥ 3 = 18 ∕ 9 = 2), producing a voltage equal to 2 × 4 = 8 V = − v(0).

At t = 0, the switch on the left closes and the switch on the right opens, producing the circuit shown in Fig. 7.67(b).

The easiest way to complete the solution is to find the Thevenin equivalent circuit as seen by the capacitor. The opencircuit voltage (with the capacitor removed) is equal to the voltage drop across the 6-Ω resistor on the left, or 10 V (the voltage drops uniformly across the 12- Ω resistor, 20 V, and across the 6- Ω resistor, 10 V). This is VTh . The resistance looking in where the capacitor was is equal to 12 ∥ 6 + 6 = 72 ∕18 + 6 = 10 Ω, which is Req. This produces the Thevenin equivalent circuit shown in Fig. 7.67(c). Matching up the boundary conditions ( v(0) = −8 V and v ( ∞ ) = 10 V) and τ = RC = 1, we get

$$v(t) = 10 - 18e^{-t} V$$

5. Evaluate. There are two ways of solving the problem using PSpice .

■ METHOD 1 One way is to first do the dc PSpice analysis to determine the initial capacitor voltage. The schematic of the revelant circuit is in Fig. 7.68(a). Two pseudocomponent VIEWPOINTs are inserted to measure the voltages at nodes 1 and 2. When the circuit is simulated, we obtain the displayed values in Fig. 7.68(a) as V ¹ = 0 V and V2 = 8 V. Thus, the initial capacitor voltage is v(0) = V 1 − V2 = −8 V. The PSpice transient analysis uses this value along with the schematic in Fig. 7.68(b). Once the circuit in Fig. 7.68(b) is drawn, we insert the capacitor initial voltage as IC = −8. We select Analysis/ Setup/Transient and set Print Step to 0.1 s and Final Step to 4 τ = 4 s. After saving the circuit, we select Analysis/Simulate to simulate the circuit. In the PSpice A/D window, we select Trace/Add and display V(R2:2) – V(R3:2) or V(C1:1) − V(C1:2) as the capacitor voltage v ( t). The plot of v ( t) is shown in Fig. 7.69. This agrees with the result ob tained by hand calculation, v ( t ) = 10 − 18 e − t V.

Figure 7.69 Response v(t) for the circuit in Fig. 7.67.

Figure 7.68

(a) Schematic for dc analysis to get v(0), (b) schematic for transient analysis used in getting the response v(t).

■ METHOD 2 We can simulate the circuit in Fig. 7.67 directly, since PSpice can handle the open and closed switches and determine the initial conditions automatically. Using this approach, the schemat ic is drawn as shown in Fig. 7.70. After drawing the circuit, we select Analysis/Setup/Transient and set Print Step to 0.1 s and Final Step to 4τ = 4 s. We save the circuit, then select Analysis/Simulate to simulate the circuit. In the PSpice A/D window, we select Trace/Add and display V(R2:2) − V(R3:2) as the capacitor voltage v(t). The plot of v(t) is the same as that shown in Fig. 7.69.

6. Satisfactory? Clearly, we have found the value of the output response v(t), as required by the problem statement. Checking does validate that solution. We can present all this as a complete solution to the problem.

The switch in Fig. 7.71 was open for a long time but closed at t = 0. If i(0) = 10A, find i(t) for t > 0 by hand and also by PSpice.

Answer: i(t) = 6 + 4 e⁻5*^t* A. The plot of i(t) obtained by PSpice analysis is shown in Fig. 7.72.

Practice Problem 7.18