4.6 SYSTEM [REALIZATION](#page-10-0)

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4.6 SYSTEM REALIZATION

We now develop a systematic method for realization (or implementation) of an arbitrary Nth-order transfer function. The most general transfer function with M = N is given by

$$H(s) = \frac{b_0 s^N + b_1 s^{N-1} + \dots + b_{N-1} s + b_N}{s^N + a_1 s^{N-1} + \dots + a_{N-1} s + a_N}$$

(4.36)

Since realization is basically a synthesis problem, there is no unique way of realizing a system. A given transfer function can be realized in many different ways. A transfer function H(s) can be realized by using integrators or differentiators along with adders and multipliers. We avoid use of differentiators for practical reasons discussed in Secs. 2.1 and 4.3-3. Hence, in our implementation, we shall use integrators along with scalar multipliers and adders. We are already familiar with representation of all these elements except the integrator. The integrator can be represented by a box with integral sign (time-domain representation, Fig. 4.19a) or by a box with transfer function 1/s (frequency-domain representation, Fig. 4.19b).

Figure 4.19 (a) Time-domain and (b) frequency-domain representations of an integrator.

4.6-1 Direct Form I Realization

Rather than realize the general Nth-order system described by Eq. (4.36), we begin with a specific case of the following third-order system and then extend the results to the Nth-order case:

$$H(s) = \frac{b_0 s^3 + b_1 s^2 + b_2 s + b_3}{s^3 + a_1 s^2 + a_2 s + a_3} = \frac{b_0 + \frac{b_1}{s} + \frac{b_2}{s^2} + \frac{b_3}{s^3}}{1 + \frac{a_1}{s} + \frac{a_2}{s^2} + \frac{a_3}{s^3}}$$

We can express H(s) as

H(s) = \underbrace{\left(b_0 + \frac{b_1}{s} + \frac{b_2}{s^2} + \frac{b_3}{s^3}\right)}_{H_1(s)} \underbrace{\left(\frac{1}{1 + \frac{a_1}{s} + \frac{a_2}{s^2} + \frac{a_3}{s^3}\right)}_{H_2(s)}}

We can realize H(s) as a cascade of transfer function H1(s) followed by H2(s), as depicted in Fig. 4.20a, where the output of H1(s) is denoted by W(s). Because of the commutative property of LTI system transfer functions in cascade, we can also realize H(s) as a cascade of H2(s) followed by H1(s), as illustrated in Fig. 4.20b, where the (intermediate) output of H2(s) is denoted by V(s).

Figure 4.20 Realization of a transfer function in two steps.

The output of H1(s) in Fig. 4.20a is given by W(s) = H1(s)X(s). Hence,

$$W(s) = \left(b_0 + \frac{b_1}{s} + \frac{b_2}{s^2} + \frac{b_3}{s^3}\right)X(s)$$

\n(4.37)

Also, the output Y(s) and the input W(s) of H2(s) in Fig. 4.20a are related by Y(s) = H2(s)W(s). Hence,

$$W(s) = \left(1 + \frac{a_1}{s} + \frac{a_2}{s^2} + \frac{a_3}{s^3}\right)Y(s)$$

\n(4.38)

Figure 4.21 Direct form I realization of an LTIC system: (a) third-order and (b) Nth-order.

We shall first realize H1(s). Equation (4.37) shows that the output W(s) can be synthesized by adding the input b0X(s) to b1(X(s)/s),b2(X(s)/s²), and b3(X(s)/s³). Because the transfer function of an integrator is 1/s, the signals X(s)/s,X(s)/s2, and X(s)/s³ can be obtained by successive integration of the input x(t). The left-half section of Fig. 4.21a shows how W(s) can be synthesized from X(s), according to Eq. (4.37). Hence, this section represents a realization of H1(s).

To complete the picture, we shall realize H2(s), which is specified by Eq. (4.38). We can rearrange Eq. (4.38) as

$$Y(s) = W(s) - \left(\frac{a_1}{s} + \frac{a_2}{s^2} + \frac{a_3}{s^3}\right) Y(s)$$

\n(4.39)

Hence, to obtain Y(s), we subtract a1Y(s)/s, a2Y(s)/s2, and a3Y(s)/s³ from W(s). We have already obtained W(s) from the first step [output of H1(s)]. To obtain signals Y(s)/s, Y(s)/s2, and Y(s)/s3, we assume that we already have the desired output Y(s). Successive integration of Y(s) yields the needed signals Y(s)/s, Y(s)/s2, and Y(s)/s3. We now synthesize the final output Y(s) according to Eq. (4.39), as seen in the right-half section of Fig. 4.21a.† The left-half section in Fig. 4.21a represents H1(s) and the right-half is H2(s). We can generalize this procedure, known as the direct form I (DFI) realization, for any value of N. This procedure requires 2N integrators to realize an Nth-order transfer function, as shown in Fig. 4.21b.

4.6-2 Direct Form II Realization

In the direct form I, we realize H(s) by implementing H1(s) followed by H2(s), as shown in Fig. 4.20a. We can also realize H(s), as shown in Fig. 4.20b, where H2(s) is followed by H1(s).

^† It may seem odd that we first assumed the existence of Y(s), integrated it successively, and then in turn generated Y(s) from W(s) and the three successive integrals of signal Y(s). This procedure poses a dilemma similar to “Which came first, the chicken or the egg?” The problem here is satisfactorily resolved by writing the expression for Y(s) at the output of the right-hand adder (at the top) in Fig. 4.21a and verifying that this expression is indeed the same as Eq. (4.38).

Figure 4.22 Direct form II realization of an Nth-order LTIC system.

This procedure is known as the direct form II realization. Figure 4.22a shows direct form II realization, where we have interchanged sections representing H1(s) and H2(s) in Fig. 4.21b. The output of H2(s) in this case is denoted by V(s). ‡

An interesting observation in Fig. 4.22a is that the input signal to both the chains of integrators is V(s). Clearly, the outputs of integrators in the left-side chain are identical to the corresponding outputs of the right-side integrator chain, thus making the right-side chain redundant. We can eliminate this chain and obtain the required signals from the left-side chain, as shown in Fig. 4.22b. This implementation halves the number of integrators to N, and, thus, is more efficient in hardware utilization than either Figs. 4.21b or 4.22a. This is the direct form II (DFII) realization.

An Nth-order differential equation with N = M has a property that its implementation requires a minimum of N integrators. A realization is canonic if the number of integrators used in the realization is equal to the order of the transfer function realized. Thus, canonic realization has no redundant integrators. The DFII form in Fig. 4.22b is a canonic realization, and is also called the direct canonic form. Note that the DFI is noncanonic.

The direct form I realization (Fig. 4.22b) implements zeros first [the left-half section represented by H1(s)] followed by realization of poles [the right-half section represented by H2(s)] of H(s). In contrast, canonic direct implements poles first followed by zeros. Although both these realizations result in the same transfer function, they generally behave differently from the viewpoint of sensitivity to parameter variations.

$$V(s) = X(s) - \left(\frac{a_1}{s} + \frac{a_2}{s^2} + \dots + \frac{a_N}{s^N}\right) V(s)$$

and

$$Y(s) = \left(b_0 + \frac{b_1}{s} + \frac{b_2}{s^2} + \dots + \frac{b_N}{s^N}\right) V(s)$$

^‡ The reader can show that the equations relating X(s),V(s), and Y(s) in Fig. 4.22a are

EXAMPLE 4.22 Canonic Direct Form Realizations

Find the canonic direct form realization of the following transfer functions:

(a)

$$\frac{5}{s+7}$$

\n(b) $\frac{s}{s+7}$
\n(c) $\frac{s+5}{s+7}$
\n(d) $\frac{4s+28}{s^2+6s+5}$

All four of these transfer functions are special cases of H(s) in Eq. (4.36).

(a) The transfer function 5/(s+7) is of the first order (N = 1); therefore, we need only one integrator for its realization. The feedback and feedforward coefficients are

$$a_1 = 7$$

and $b_0 = 0$ , $b_1 = 5$

The realization is depicted in Fig. 4.23a. Because N = 1, there is a single feedback connection from the output of the integrator to the input adder with coefficient a¹ = 7. For N = 1, generally, there are N + 1 = 2 feedforward connections. However, in this case, b⁰ = 0, and there is only one feedforward connection with coefficient b¹ = 5 from the output of the integrator to the output adder. Because there is only one input signal to the output adder, we can do away with the adder, as shown in Fig. 4.23a.

(b)

$$H(s) = \frac{s}{s+7}$$

In this first-order transfer function, b¹ = 0. The realization is shown in Fig. 4.23b. Because there is only one signal to be added at the output adder, we can discard the adder.

(c)

$$H(s) = \frac{s+5}{s+7}$$

The realization appears in Fig. 4.23c. Here H(s) is a first-order transfer function with a¹ = 7 and b⁰ = 1, b¹ = 5. There is a single feedback connection (with coefficient 7) from the integrator output to the input adder. There are two feedforward connections (Fig. 4.23c).†

$$H(s) = 1 - \frac{2}{s+7}$$

We now realize H(s) as a parallel combination of two transfer functions, as indicated by this equation.

^† When ^{M = N} (as in this case), ^H(s) can also be realized in another way by recognizing that

$$f_{\rm{max}}$$

(d)

$$H(s) = \frac{4s + 28}{s^2 + 6s + 5}$$

This is a second-order system with b⁰ = 0, b¹ = 4, b² = 28, a¹ = 6, and a² = 5. Figure 4.23d shows a realization with two feedback connections and two feedforward connections.

DR ILL 4.11 Canonic Direct Form Realization

Give the canonic direct realization of

$$H(s) = \frac{2s}{s^2 + 6s + 25}$$

4.6-3 Cascade and Parallel Realizations

An Nth-order transfer function H(s) can be expressed as a product or a sum of N first-order transfer functions. Accordingly, we can also realize H(s) as a cascade (series) or parallel form of these N first-order transfer functions. Consider, for instance, the transfer function in part (d) of Ex. 4.22.

$$H(s) = \frac{4s + 28}{s^2 + 6s + 5}$$

We can express H(s) as

$$H(s) = \frac{4s + 28}{(s+1)(s+5)} = \underbrace{\left(\frac{4s + 28}{s+1}\right)}_{H_1(s)} \underbrace{\left(\frac{1}{s+5}\right)}_{H_2(s)}$$

We can also express H(s) as a sum of partial fractions as

$$H(s) = \frac{4s + 28}{(s+1)(s+5)} = \underbrace{\frac{6}{s+1}}_{H_3(s)} - \underbrace{\frac{2}{s+5}}_{H_4(s)}$$

These equations give us the option of realizing H(s) as a cascade of H1(s) and H2(s), as shown in Fig. 4.24a, or a parallel of H3(s) and H4(s), as depicted in Fig. 4.24b. Each of the first-order transfer functions in Fig. 4.24 can be implemented by using canonic direct realizations, discussed earlier.

This discussion by no means exhausts all the possibilities. In the cascade form alone, there are different ways of grouping the factors in the numerator and the denominator of H(s), and each grouping can be realized in DFI or canonic direct form. Accordingly, several cascade forms are possible. In Sec. 4.6-4, we shall discuss yet another form that essentially doubles the numbers of realizations discussed so far.

From a practical viewpoint, parallel and cascade forms are preferable because parallel and certain cascade forms are numerically less sensitive than canonic direct form to small parameter variations in the system. Qualitatively, this difference can be explained by the fact that in a canonic realization all the coefficients interact with each other, and a change in any coefficient will be magnified through its repeated influence from feedback and feedforward connections. In a parallel realization, in contrast, the change in a coefficient will affect only a localized segment; the case with a cascade realization is similar.

In the examples of cascade and parallel realization, we have separated H(s) into first-order factors. For H(s) of higher orders, we could group H(s) into factors, not all of which are necessarily of the first order. For example, if H(s) is a third-order transfer function, we could realize this function as a cascade (or a parallel) combination of a first-order and a second-order factor.

Figure 4.24 Realization of (4s +28)/[(s+1)(s+5)]: (a) cascade form and (b) parallel form.

REALIZATION OF COMPLEX CONJUGATE POLES

The complex poles in H(s) should be realized as a second-order (quadratic) factor because we cannot implement multiplication by complex numbers. Consider, for example,

$$H(s) = \frac{10s + 50}{(s+3)(s^2+4s+13)}$$

=

$$\frac{10s + 50}{(s+3)(s+2-j3)(s+2+j3)}$$

=

$$\frac{2}{s+3} - \frac{1+j2}{s+2-j3} - \frac{1-j2}{s+2+j3}$$

We cannot realize first-order transfer functions individually with the poles −2 ± j3 because they require multiplication by complex numbers in the feedback and the feedforward paths. Therefore, we need to combine the conjugate poles and realize them as a second-order transfer function.† In the present example, we can create a cascade realization from H(s) expressed in product form as

$$H(s) = \left(\frac{10}{s+3}\right) \left(\frac{s+5}{s^2+4s+13}\right)$$

Similarly, we can create a parallel realization from H(s) expressed in sum form as

$$H(s) = \frac{2}{s+3} - \frac{2s-8}{s^2+4s+13}$$

REALIZATION OF REPEATED POLES

When repeated poles occur, the procedure for canonic and cascade realization is exactly the same as before. For a parallel realization, however, the procedure requires special handling, as explained in Ex. 4.23.

EXAMPLE 4.23 Parallel Realization

Determine the parallel realization of

$$H(s) = \frac{7s^2 + 37s + 51}{(s+2)(s+3)^2} = \frac{5}{s+2} + \frac{2}{s+3} - \frac{3}{(s+3)^2}$$

This third-order transfer function should require no more than three integrators. But if we try to realize each of the three partial fractions separately, we require four integrators because of the one second-order term. This difficulty can be avoided by observing that the terms 1/(s+3) and

^† It is possible to realize complex, conjugate poles indirectly by using a cascade of two first-order transfer functions and feedback. A transfer function with poles −a ± jb can be realized by using a cascade of two identical first-order transfer functions, each having a pole at −a (see Prob. 4.6-15).

Figure 4.25 Parallel realization of (7s² +37s +51)/((s +2)(s +3)2).

1/(s + 3)² can be realized with a cascade of two subsystems, each having a transfer function 1/(s + 3), as shown in Fig. 4.25. Each of the three first-order transfer functions in Fig. 4.25 may now be realized as in Fig. 4.23.

DR ILL 4.12 Canonic, Cascade, and Parallel Realizations

Find the canonic, cascade, and parallel realization of

$$H(s) = \frac{s+3}{s^2 + 7s + 10} = \left(\frac{s+3}{s+2}\right)\left(\frac{1}{s+5}\right)$$

4.6-4 Transposed Realization

Two realizations are said to be equivalent if they have the same transfer function. A simple way to generate an equivalent realization from a given realization is to use its transpose. To generate a transpose of any realization, we change the given realization as follows:

• 1. Reverse all the arrow directions without changing the scalar multiplier values.
• 2. Replace pickoff nodes by adders and vice versa.
• 3. Replace the input X(s) with the output Y(s) and vice versa.

Figure 4.26a shows the transposed version of the canonic direct form realization in Fig. 4.22b found according to the rules just listed. Figure 4.26b is Fig. 4.26a reoriented in the conventional form so that the input X(s) appears at the left and the output Y(s) appears at the right. Observe that this realization is also canonic.

Rather than prove the theorem on equivalence of the transposed realizations, we shall verify that the transfer function of the realization in Fig. 4.26b is identical to that in Eq. (4.36).

Figure 4.26 Realization of an Nth-order LTI transfer function in the transposed form.

Figure 4.26b shows that Y(s) is being fed back through N paths. The fed-back signal appearing at the input of the top adder is

$$\left(\frac{-a_1}{s} + \frac{-a_2}{s^2} + \cdots + \frac{-a_{N-1}}{s^{N-1}} + \frac{-a_N}{s^N}\right)Y(s)$$

The signal X(s), fed to the top adder through N +1 forward paths, contributes

$$\left(b_0 + \frac{b_1}{s} + \cdots + \frac{b_{N-1}}{s^{N-1}} + \frac{b_N}{s^N}\right)X(s)$$

The output Y(s) is equal to the sum of these two signals (feed forward and feed back). Hence,

$$Y(s) = \left(\frac{-a_1}{s} + \frac{-a_2}{s^2} + \dots + \frac{-a_{N-1}}{s^{N-1}} + \frac{-a_N}{s^N}\right)Y(s) + \left(b_0 + \frac{b_1}{s} + \dots + \frac{b_{N-1}}{s^{N-1}} + \frac{b_N}{s^N}\right)X(s)$$

Transporting all the Y(s) terms to the left side and multiplying throughout by sN, we obtain

$$(sN + a1sN-1 + \dots + aN-1s + aN)Y(s) = (b0sN + b1sN-1 + \dots + bN-1s + bN)X(s)$$

Consequently,

$$H(s) = \frac{Y(s)}{X(s)} = \frac{b_0 s^N + b_1 s^{N-1} + \dots + b_{N-1} s + b_N}{s^N + a_1 s^{N-1} + \dots + a_{N-1} s + a_N}$$

Hence, the transfer function H(s) is identical to that in Eq. (4.36).

We have essentially doubled the number of possible realizations. Every realization that was found earlier has a transpose. Note that the transpose of a transpose results in the same realization.

EXAMPLE 4.24 Transposed Realizations

Find the transpose canonic direct realizations for parts (a) and (d) of Ex. 4.22 (Figs. 4.23c and 4.23d). The transfer functions are:

(a)

$$\frac{s+5}{s+7}$$

\n(b) $\frac{4s+28}{s^2+6s+5}$

Both these realizations are special cases of the one in Fig. 4.26b.

(a) In this case, N = 1 with a¹ = 7,b⁰ = 1,b¹ = 5. The desired realization can be obtained by transposing Fig. 4.23c. However, we already have the general model of the transposed realization in Fig. 4.26b. The desired solution is a special case of Fig. 4.26b with N = 1 and a¹ = 7,b⁰ = 1,b¹ = 5, as shown in Fig. 4.27a.

(b) In this case, N = 2 with b⁰ = 0, b¹ = 4, b² = 28, a¹ = 6, a² = 5. Using the model of Fig. 4.26b, we obtain the desired realization, as shown in Fig. 4.27b.

Figure 4.27 Transposed canonic direct form realizations of (a) (s+5)/(s+7) and (b) (4s+28)/(s² +6s+5).

DR ILL 4.13 Transposed Realizations

Find the transposed DFI and transposed canonic direct (TDFII) realizations of H(s) in Drill 4.11

4.6-5 Using Operational Amplifiers for System Realization

In this section, we discuss practical implementation of the realizations described in Sec. 4.6-4. Earlier we saw that the basic elements required for the synthesis of an LTIC system (or a given transfer function) are (scalar) multipliers, integrators, and adders. All these elements can be realized by operational amplifier (op-amp) circuits.

OPERATIONAL AMPLIFIER CIRCUITS

Figure 4.28 shows an op-amp circuit in the frequency domain (the transformed circuit). Because the input impedance of the op amp is infinite (very high), all the current I(s) flows in the feedback path, as illustrated. Moreover Vx(s), the voltage at the input of the op amp, is zero (very small) because of the infinite (very large) gain of the op amp. Therefore, for all practical purposes,

$$Y(s) = -I(s)Z_f(s)$$

Moreover, because vx ≈ 0,

$$I(s) = \frac{X(s)}{Z(s)}$$

Substitution of the second equation in the first yields

$$Y(s) = -\frac{Z_f(s)}{Z(s)}X(s)$$

Therefore, the op-amp circuit in Fig. 4.28 has the transfer function

$$H(s) = -\frac{Z_f(s)}{Z(s)}$$

By properly choosing Z(s) and Zf(s), we can obtain a variety of transfer functions, as the following development shows.

Figure 4.28 A basic inverting configuration op-amp circuit.

THE SCALAR MULTIPLIER

If we use a resistor Rf in the feedback and a resistor R at the input (Fig. 4.29a), then Zf(s) = Rf , Z(s) = R, and

$$H(s) = -\frac{R_f}{R}$$

The system acts as a scalar multiplier (or an amplifier) with a negative gain Rf /R. A positive gain can be obtained by using two such multipliers in cascade or by using a single noninverting amplifier, as depicted in Fig. 4.16c. Figure 4.29a also shows the compact symbol used in circuit diagrams for a scalar multiplier.

THE INTEGRATOR

If we use a capacitor C in the feedback and a resistor R at the input (Fig. 4.29b), then Zf(s) = 1/Cs, Z(s) = R, and

$$H(s) = \left(-\frac{1}{RC}\right)\frac{1}{s}$$

The system acts as an ideal integrator with a gain −1/RC. Figure 4.29b also shows the compact symbol used in circuit diagrams for an integrator.

Figure 4.29 (a) Op-amp inverting amplifier. (b) Integrator.

Figure 4.30 Op-amp summing and amplifying circuit.

THE ADDER

Consider now the circuit in Fig. 4.30a with r inputs X1(s), X2(s), … , Xr(s). As usual, the input voltage Vx(s) 0 because the op-amp gain → ∞. Moreover, the current going into the op amp is very small ( 0) because the input impedance → ∞. Therefore, the total current in the feedback resistor Rf is I1(s)+I2(s)+···+Ir(s). Moreover, because Vx(s) = 0,

$$I_j(s) = \frac{X_j(s)}{R_j}$$

$j = 1, 2, ..., r$

Also,

$$Y(s) = -R_f[I_1(s) + I_2(s) + \dots + I_r(s)]$$

=

$$-\left[\frac{R_f}{R_1}X_1(s) + \frac{R_f}{R_2}X_2(s) + \dots + \frac{R_f}{R_r}X_r(s)\right]$$

= $k_1X_1(s) + k_2X_2(s) + \dots + k_rX_r(s)$

where

$$k_i = \frac{-R_f}{R_i}$$

Clearly, the circuit in Fig. 4.30 serves an adder and an amplifier with any desired gain for each of the input signals. Figure 4.30b shows the compact symbol used in circuit diagrams for an adder with r inputs.

EXAMPLE 4.25 Op-Amp Realization

Use op-amp circuits to realize the canonic direct form of the transfer function

$$H(s) = \frac{2s+5}{s^2+4s+10}$$

Figure 4.31 Op-amp realization of a second-order transfer function (2s+5)/(s² +4s +10).

The basic canonic realization is shown in Fig. 4.31a. The same realization with horizontal reorientation is shown in Fig. 4.31b. Signals at various points are also indicated in the realization. For convenience, we denote the output of the last integrator by W(s). Consequently, the signals at the inputs of the two integrators are sW(s) and s2W(s), as shown in Figs. 4.31a and 4.31b. Op-amp elements (multipliers, integrators, and adders) change the polarity of the output signals. To incorporate this fact, we modify the canonic realization in Fig. 4.31b to that depicted in Fig. 4.31c. In Fig. 4.31b, the successive outputs of the adder and the integrators are s2W(s),sW(s), and W(s), respectively. Because of polarity reversals in op-amp circuits, these outputs are −s2W(s),sW(s), and −W(s), respectively, in Fig. 4.31c. This polarity reversal requires corresponding modifications in the signs of feedback and feedforward gains. According to Fig. 4.31b,

$$s^2W(s) = X(s) - 4sW(s) - 10W(s)$$

Therefore,

$$-s^2W(s) = -X(s) + 4sW(s) + 10W(s)$$

Because the adder gains are always negative (see Fig. 4.30b), we rewrite the foregoing equation as

$$-s2W(s) = -1[X(s)] - 4[-sW(s)] - 10[-W(s)]$$

Figure 4.31c shows the implementation of this equation. The hardware realization appears in Fig. 4.31d. Both integrators have a unity gain, which requires RC = 1. We have used R = 100 k and C = 10 µF. The gain of 10 in the outer feedback path is obtained in the adder by choosing the feedback resistor of the adder to be 100 k and an input resistor of 10 k. Similarly, the gain of 4 in the inner feedback path is obtained by using the corresponding input resistor of 25 k. The gains of 2 and 5, required in the feedforward connections, are obtained by using a feedback resistor of 100 k and input resistors of 50 and 20 k, respectively.†

The op-amp realization in Fig. 4.31 is not necessarily the one that uses the fewest op amps. This example is given just to illustrate a systematic procedure for designing an op-amp circuit of an arbitrary transfer function. There are more efficient circuits (such as Sallen–Key or biquad) that use fewer op amps to realize a second-order transfer function.

DR ILL 4.14 Transfer Functions of Op-Amp Circuits

Show that the transfer functions of the op-amp circuits in Figs. 4.32a and 4.32b are H1(s) and H2(s), respectively, where

$$H_1(s) = \frac{-R_f}{R} \left( \frac{a}{s+a} \right) \qquad a = \frac{1}{R_f C_f}$$ $$H_2(s) = -\frac{C}{C_f} \left( \frac{s+b}{s+a} \right) \qquad a = \frac{1}{R_f C_f} \qquad b = \frac{1}{RC}$$

^† It is possible to avoid the two inverting op amps (with gain ⁻1) in Fig. 4.31d by adding signal sW(s) to the input and output adders directly, using the noninverting amplifier configuration in Fig. 4.16d.