Example 8.12

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$$v_{ot} = e^{-t}(A \cos 2t + B \sin 2t)$$

(8.11.8)

where A and B are unknown constants to be determined.

As t → ∞, the circuit reaches the steady-state condition, and the capacitors can be replaced by open circuits. Since no current flows through C1 and C2 under steady-state conditions and no current can enter the input terminals of the ideal op amp, current does not flow through R1 and R2.

Thus,

$$v_o(\infty) = v_1(\infty) = v_s$$

The steady-state response is then

$$v_{\text{oss}} = v_o(\infty) = v_s = 10 \text{ mV}, \qquad t > 0 \tag{8.11.9}$$

The complete response is

$$v_o(t) = v_{ot} + v_{oss} = 10 + e^{-t}(A \cos 2t + B \sin 2t) \text{ mV} \qquad (8.11.10)$$

To determine A and B, we need the initial conditions. For t < 0, vs = 0, so that

$$v_o(0^-) = v_2(0^-) = 0$$

For t > 0, the source is operative. However, due to capacitor voltage continuity,

$$v_o(0^+) = v_2(0^+) = 0 \tag{8.11.11}$$

From Eq. (8.11.3),

$$v_1(0^+) = v_2(0^+) + v_o(0^+) = 0$$

and, hence, from Eq. (8.11.2),

$$\frac{dv_o(0^+)}{dt} = \frac{v_1 - v_o}{R_2 C_1} = 0$$

\n(8.11.12)

We now impose Eq. (8.11.11) on the complete response in Eq. (8.11.10) at t = 0, for

$$0 = 10 + A \qquad \Rightarrow \qquad A = -10 \tag{8.11.13}$$

Taking the derivative of Eq. (8.11.10),

___ dv^o dt = e^−t (−A cos 2t − B sin 2t − 2A sin 2t + 2B cos 2t)

Setting t = 0 and incorporating Eq. (8.11.12), we obtain

$$0 = -A + 2B \tag{8.11.14}$$

From Eqs. (8.11.13) and (8.11.14), A = −10 and B = −5. Thus, the step response becomes

$$v_o(t) = 10 - e^{-t}(10\cos 2t + 5\sin 2t) \text{ mV}, \qquad t > 0$$

In the op amp circuit shown in Fig. 8.34, vs = 25u(t) V, find vo(t) for t > 0. Assume that R1 = R2 = 10 kΩ, C1 = 20 μF, and C2 = 100 μF.

Answer:

$$(25 - 31.25e^{-t} + 6.25e^{-5t})$$

V, $t > 0$ .

8.9 PSpice Analysis of RLC Circuits RLC circuits can be analyzed with great ease using PSpice, just like the

RC or RL circuits of Chapter 7. The following two examples will illustrate this. The reader may review Section D.4 in Appendix D on PSpice for transient analysis.

Example 8.12

The input voltage in Fig. 8.35(a) is applied to the circuit in Fig. 8.35(b). Use PSpice to plot v(t) for 0 < t < 4 s.

Solution:

• 1. Define. As true with most textbook problems, the problem is clearly defined.
• 2. Present. The input is equal to a single square wave of amplitude 12 V with a period of 2 s. We are asked to plot the output, using PSpice.
• 3. Alternative. Since we are required to use PSpice, that is the only alternative for a solution. However, we can check it using the technique illustrated in Section 8.5 (a step response for a series RLC circuit).
• 4. Attempt. The given circuit is drawn using Schematics as in Fig. 8.36. The pulse is specified using VPWL voltage source, but VPULSE could be used instead. Using the piecewise linear function, we set the attributes of VPWL as T1 = 0, V1 = 0, T2 = 0.001, V2 = 12, and so forth, as shown in Fig. 8.36. Two voltage markers are inserted to plot the input and output voltages. Once the circuit is drawn and the attributes are set, we select Analysis/Setup/Transient to open up the Transient Analysis dialog box. As a parallel RLC circuit, the roots of the characteristic equation are −1 and −9. Thus, we may set Final Time as 4 s (four times the magnitude of the lower root). When the schematic

is saved, we select Analysis/Simulate and obtain the plots for the input and output voltages under the PSpice A/D window as shown in Fig. 8.37.

Now we check using the technique from Section 8.5. We can start by realizing the Thevenin equivalent for the resistor-source combination is VTh = 12∕2 (the open circuit voltage divides equally across both resistors) = 6 V. The equivalent resistance is 30 Ω (60 ‖ 60). Thus, we can now solve for the response using R = 30 Ω, L = 3 H, and C = (1∕27) F.

We first need to solve for α and ω0:

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